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Low-Voltage CMOS 8-Bit High-Speed Analog-to-Digital Converter
April 2==2 1
XRD87L75
FEATURES
* 8-Bit Resolution * Up to 10MHz Sampling Rate * Internal S/H Function * Single Supply: 3.3V * VIN DC Range: 0V to VDD * VREF DC Range: 1V to VDD * Low Power: 25mW typ. (excluding reference) * Latch-Up Free
* ESD Protection: 2000V Minimum * Small 20-Pin SOIC/SSOP Packages
APPLICATIONS * Digital Color Copiers
* Cellular Telephones * CCD-Based Systems * Hardware Scanners * Video Capture Boards
GENERAL DESCRIPTION The XRD87L75 is an 8-bit Analog-to-Digital Converter in a small 20-pin SOIC/SSOP package. Designed using an advanced 3.3V CMOS process, this part offers excellent performance, low power consumption and latch-up free operation. This device uses a two-step flash architecture to maintain low power consumption at high conversion rates. The input circuitry of the XRD87L75 includes an on-chip S/H function and allows the user to digitize analog input signals between AGND and AVDD. Careful design and chip layout have achieved a low analog input capacitance. This reduces "kickback" and eases the requirements of the buffer/amplifier used to drive the XRD87L75.
The designer can choose the internally generated reference voltages by connecting VRB to VRBS and VRT to VRTS , or provide external reference voltages to the VRB and VRT pins. The internal reference generates 0.4V at VRB and 1.72V at VRT. Providing external reference voltages allows easy interface to any input signal range between GND and VDD. This also allows the system to adjust these voltages to cancel zero scale and full scale errors, or to change the input range as needed. The device operates from a single +3.3V supply. Power consumption is 25mW at FS = 6MHz. Specified for operation over the commercial / industrial (-40 to +85C) temperature range, the XRD87L75 is available in Surface Mount (SOIC), Shrink Small Outline (SSOP) and Plastic Dual-In-line (PDIP) Packages.
SIMPLIFIED BLOCK AND TIMING DIAGRAM
Rev. 1.00 EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 * (510) 668-7000 * FAX (510) 668-7017
XRD87L75
ORDERING INFORMATION
Package Type SOIC PDIP SSOP Temperature Range -40 to +85C -40 to +85C -40 to +85C DNL (LSB) +/-0.5 +/-0.5 +/-0.5 INL (LSB) +/-1.5 +/-1.5 +/-1.5
Part No. XRD87L75AID XRD87L75AIP XRD87L75AIU
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
20-Pin PDIP (300 MIL) - P20
20-Pin SOIC (Jedec, 300 MIL) - D20 20-Pin SSOP (5.3mm) - U20
PIN OUT DEFINITIONS
PIN NO. 1 2 3 4 5 6 7 8 9 10 NAME DGND DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DVDD DESCRIPTION Digital Ground Data Output Bit 0 (LSB) Data Output Bit 1 Data Output Bit 2 Data Output Bit 3 Data Output Bit 4 Data Output Bit 5 Data Output Bit 6 Data Output Bit 7 (MSB) Digital Power Supply PIN NO. 11 12 13 14 15 16 17 18 19 20 NAME CLK DVDD VRTS VRT AVDD VIN AGND VRBS VRB DGND DESCRIPTION Sample Clock Digital Power Supply Generates 1.72V if tied to VRT Top Reference Analog Power Supply Analog Input Analog Ground Generates 0.4V if tied to VRB Bottom Reference Digital Ground
Rev. 1.00
2
XRD87L75
ELECTRICAL CHARACTERISTICS TABLE UNLESS OTHERWISE SPECIFIED: AVDD = DVDD = 3.3V, FS = 6MHz (50% DUTY CYCLE), VRT = 2.5V, VRB = 0.5V, TA = 25C
25C Parameter KEY FEATURES Resolution Sampling Rate ACCURACY Differential Non-Linearity Integral Non-Linearity Zero Scale Error Full Scale Error REFERENCE VOLTAGES Positive Ref. Voltage Negative Ref. Voltage Differential Ref. Voltage3 Ladder Resistance Ladder Temp. Coefficient Self Bias 1 Short VRB and VRBS Short VRT and VRTS Self Bias 2 VRB = AGND, Short VRT and VRTS ANALOG INPUT Input Bandwidth (-1 dB)2, 4 Input Voltage Range Input Capacitance Aperture Delay
2 5
Symbol
Min 8
Typ
Max
Units Bits
Test Conditions/Comments
FS DNL INL EZS EFS VRT VRB V REF RL RTCO VRB VRT-VRB VRT
0.1
6 +/-0.3 +/-0.75 +3 -2 2.5
10 +/-0.5 +/-1.5
MHz LSB LSB LSB LSB Best Fit Line (Max INL - Min INL)/2
AVDD AVDD
V V V VREF = VRT - VRB
AGND 1.0 245
0.5 350 2000 0.4 1.72 1.5 550
ppm/C V V V
BW VIN CIN tAP VIH VIL IIN 2.5 VRB
50 VRT 16 4
MHz V pF ns V 0.5 V VIN =DGND to DVDD
DIGITAL INPUTS Logical "1" Voltage Logical "0" Voltage DC Leakage Current 6 CLK Input Capacitance Clock Timing ( See Figure 1.)7 Clock Period High Pulse Width Low Pulse Width DIGITAL OUTPUTS Logical "1" Voltage Logical "0" Voltage Data Valid Delay 8 VOH VOL t DL 12 2.5 0.5 V V ns 1/FS tPWH tPWL 100 50 50 166 83 83 ns ns ns C OUT =15 pF I LOAD = 1 mA I LOAD = 1 mA
5 5
A
pF
Rev. 1.00
3
XRD87L75
ELECTRICAL CHARACTERISTICS TABLE (CONT'D) UNLESS OTHERWISE SPECIFIED: AVDD = DVDD = 3.3V, FS = 6MHz (50% DUTY CYCLE), VRT = 2.5V, VRB = 0.5V, TA = 25C
25C Parameter AC PARAMETERS Differential Gain Error Differential Phase Error POWER SUPPLIES Operating Voltage (AVDD, DVDD)9 Current (AGND + DGND) VDD I DD 3 3.3 8 3.6 12 V mA Does not include ref. current dG dPH 2 1 % Degree FS = 4 x NTSC FS = 4 x NTSC Symbol Min Typ Max Units Test Conditions/Comments
NOTES 1. The difference between the measured and the ideal code width (VREF/256) is the DNL error (Figure 3). The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage (Figure 4). Accuracy is a function of the sampling rate (FS). 2. Guaranteed, not tested. 3. Specified values guarantee functionality. Refer to other parameters for accuracy. 4. -1dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within the specified bandwidth. 5. See VIN input equivalent circuit (Figure 5). Switched capacitor analog input requires driver with low output resistance. 6. All inputs have diodes to DVDD and DGND. Input DC currents will not exceed specified limits for any input voltage between DGND and DVDD . 7. tR , tF should be limited to >5ns for best results. 8. Depends on the RC load connected to the output pin. 9. AGND & DGND pins are connected through the silicon substrate. Connect together at the package and to the analog ground plane.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2, 3
VDD to GND ....................................................... 5.5V VRT & V RB ......................... VDD +0.5 to GND -0.5V VIN ..................................... VDD +0.5 to GND -0.5V All Inputs ............................ VDD +0.5 to GND -0.5V All Outputs ......................... VDD +0.5 to GND -0.5V Storage Temperature .........................-65 to +150C Lead Temperature (Soldering 10 seconds) ... +300C Package Power Dissipation Rating @ 75C PDIP, SOIC, SSOP .............................. 650mW Derates above 75C ............................. 9mW/C
NOTES: 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100A for less than 100ms. 3. VDD refers to AVDD and DVDD. GND refers to AGND and DGND.
Rev. 1.00
4
XRD87L75
Figure 1. XRD87L75 Timing Diagram
Figure 2. DNL Measurement
Figure 3. INL Error Calculation
Figure 4. Equivalent Input Circuit
Figure 5. Typical Circuit Connections
Rev. 1.00
5
XRD87L75
APPLICATION NOTES
Signals should not exceed AVDD +0.5V or go below AGND -0.5V or DVDD +0.5V or DGND -0.5V. All pins have internal protection diodes that will protect them from short transients (<100s) outside the supply range. AGND and DGND pins are connected internally through the P- substrate. DC voltage differences between these pins will cause undesirable internal substrate currents. The power supply (AVDD) and reference voltage (VRT & VRB) pins should be decoupled with 0.1F and 10F capacitors to AGND, placed as close to the chip as possible. The digital outputs should not drive long wires or buses. The capacitive coupling and reflections will contribute noise to the conversion. To avoid timing errors, use the rising edge of the sample clock (CLK) to latch data from the XRD87L75 to other parts of the system. The reference can be biased internally by shorting VRT to VRTS and VRB to VRBS. This will generate 0.4V at VRB and 1.72V at VRT (see Figure 5.). If the internal reference pins VRTS and/or VRBS are not used they should be left unconnected.
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 Code 160 192
Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V Fs = 6MHz o Ta = 25 C
DNL (LSB)
224
256
Graph 1. DNL vs. Code
Rev. 1.00
6
XRD87L75
1.0 0.8 0.6 0.4 0.2 INL (LSB) 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 Code 160 192 224 256 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V Fs = 6MHz o Ta = 25 C
Graph 2. INL vs. Code
1.0 0.8 0.6 0.4 POS DNL 0.2 DNL (LSB) 0.0 -0.2 NEG DNL -0.4 -0.6 -0.8 -1.0 0.10 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V Ta = 25 oC
1.00 Fs (MHz)
10.00
100.00
Graph 3. DNLvs. Sampling Frequency
Rev. 1.00
7
XRD87L75
1.0 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V o Ta = 25 C 0.8
0.6 INL (LSB) 0.4 0.2 0.0 0.10
1.00 Fs (MHz)
10.00
100.00
Graph 4. Best Fit INL vs. Sampling Frequency
20
Ta = 25 oC
16 Vdd = 3.6V
Vdd = 3.3V 12 Idd (mA) Vdd = 3.0V 8
Vdd = 2.7V
4
0 0 5 10 15 Fs (MHz) 20 25 30
Graph 5. IDD vs. Sampling Frequency
Rev. 1.00
8
XRD87L75
14 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V
12
10 Fs = 10MHz Idd (mA) 8 Fs = 6MHz Fs = 2MHz 6
4
2
0 -60 -40 -20 0 20 Temperature (C) 40 60 80 100
Graph 6. Supply Current vs. Temperature
550
Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V
500
Ladder Resistance (ohm)
450
400
350
300
250 -60 -40 -20 0 20 Temperature (C) 40 60 80 100
Graph 7. Ladder Resistance vs. Temperature
Rev. 1.00
9
XRD87L75
50 45 40 35 30 SNR (dB) 25 20 15 10 5 0 0.01 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V Fs = 6MHz Ta = 25oC
0.1 Fin (MHz)
1
10
Graph 8. SNR vs. Input Frequency
50 45 40 35 30 SINAD (dB) 25 20 15 10 5 0 0.01
Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V Fs = 6MHz Ta = 25oC
0.1 Fin (MHz)
1
10
Graph 9. SINAD vs. Input Frequency
Rev. 1.00
10
XRD87L75
Graph 10. FFT Plot
80 60 40 20 0 -20 -40 -60 -80 -100 -120 0.0 0.5 1.0 1.5 Frequency (MHz) 2.0 2.5 3.0 Vdd = 3.3V Vrt = 2.5V Vrb = 0.5V Fs = 6MHz Fin = 500KHz
Amplitude (dB)
Graph 10. FFT Plot
Rev. 1.00
11
XRD87L75
20 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP)
REV. 1.00
20 1 D
11 10 E1
E
A2 Seating Plane A L A1 B e B1 C
eA eB
Note: The control dimension is the inch column
INCHES SYMBOL A A1 A2 B B1 C D E E1 e eA eB L a 0.310 0.115 0 MIN 0.145 0.015 0.115 0.014 0.030 0.008 0.925 0.300 0.240 MAX 0.210 0.070 0.195 0.024 0.070 0.014 1.060 0.325 0.280 0.100 BSC 0.300 BSC 0.430 0.160 15 7.87 2.92 0 MIN 3.68 0.38 2.92 0.36 0.76 0.20 23.50 7.62 6.10
MILLIMETERS MAX 5.33 1.78 4.95 0.56 1.78 0.38 26.92 8.26 7.11 2.54 BSC 7.62 BSC 10.92 4.06 15
Rev. 1.00
12
XRD87L75
20 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC)
REV. 1.00
D
20
11
E
1 10
H
C A Seating Plane e B A1 L
NOTE: The control dimension is the millimeter column
INCHES SYMBOL A A1 B C D E e H L a 0.394 0.016 0 MIN 0.093 0.004 0.013 0.009 0.496 0.291 MAX 0.104 0.012 0.020 0.013 0.512 0.299 0.050 BSC 0.419 0.050 8
MILLIMETERS MIN MAX 2.35 0.10 0.33 0.23 12.60 7.40 1.27 BSC 10.00 0.40 0 10.65 1.27 8 2.65 0.30 0.51 0.32 13.00 7.60
Rev. 1.00
13
XRD87L75
20 LEAD SHRINK SMALL OUTLINE PACKAGE (5.3 mm SSOP)
REV. 2.00
D
20
11
E
1 10
H
C A2 Seating Plane e B A1 L A
Note: The control dimension is the millimeter column
INCHES SYMBOL A A1 A2 B C D E e H L a 0.292 0.022 0 MIN 0.067 0.002 0.065 0.009 0.004 0.272 0.197 MAX 0.079 0.006 0.073 0.015 0.010 0.296 0.221 0.0256 BSC 0.323 0.037 8 7.40 0.55 0 MIN 1.70 0.05 1.65 0.22 0.09 6.90 5.00
MILLIMETERS MAX 2.00 0.15 1.85 0.38 0.25 7.50 5.60 0.65 BSC 8.20 0.95 8
Rev. 1.00
14
XRD87L75
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 2002 EXAR Corporation
Datasheet April 2002 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. Rev. 1.00
15

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